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| موضوع: كتاب Make - FPGAs - Turning Software into Hardware with Eight Fun & Easy DIY Projects السبت 03 فبراير 2024, 10:36 pm | |
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أخواني في الله أحضرت لكم كتاب Make - FPGAs - Turning Software into Hardware with Eight Fun & Easy DIY Projects David Romano
و المحتوى كما يلي :
Table of ContentsDesign 25 Peripheral Breadboard 25 FPGA Circuit Schematic Design Entry 27 FPGA Circuit HDL Design Entry 45 Simulation 60 Build . 65 Creating the Constraints File 68 Open Kelly Setup 72 Setup Test 73 Clock Frequency Experimentation . 75 Takeaways 76 3. That’s Refreshing 79 Stopwatch Concept . 79 How It Works . 80 Design 82 Peripheral Breadboard 83 FPGA Circuit 84 Digital Clock Manager (DCM) 87 Verilog Code and Concurrency 90 Simulation 98 Build 100 Assigning Physical I/O . 100 Takeaways . 101 4. Testing 1, 2, 3, 4 . 103 The Test Bench . 103 Test Bench Anatomy . 104 Reuse 105 Running the Test Bench Project . 105 Step 1: Selection and Download of Core 105 Step 2: Documentation 107 iv Make: FPGAsStep 3: RTL 109 Step 4: Adding Test Bench Files and Running the Simulation 112 Exploring the Test Bench Project 116 Overview 116 Takeaways . 124 5. It Does Not Compute . 125 The CARDIAC Computer Model . 125 Getting Started with VTACH 128 Numato Elbert V2 Setup 130 Modifications 134 Step 1: Device Section . 134 Step 2: Pin Assignments 135 Step 3: Clocking . 137 Step 4: I/O Polarity . 138 Step 5: Memory Block Update 141 Design, Build, and Simulation 145 Simulation 145 Building and Running 150 Programing and Assembler . 151 Takeaways . 153 6. It’s a Small World! 155 System on Chip 155 SoC Architecture . 157 DesignLab . 160 Installation 160 Papilio DUO Setup . 161 Step 1: Power Up 162 Step 2: Select COM Port 162 Step 3: Create Project 164 Step 4: Associate Circuit 164 Table of Contents vStep 5: Load FPGA Bit File 166 Step 6: Compile and Upload Sketch 168 Getting Started with the DesignLab Video-Audio Player . 169 How It Works 169 Design . 171 Step 1: Create New DesignLab Project 171 Step 2: Edit Your Design in Xilinx ISE 172 Step 3: Add VGA Adapter Block . 175 Step 4: Add Audio Blocks . 175 Step 5: Implement and Generate Bit File 177 Step 6: Create Sketch, Load, and Run . 178 Experiments . 179 Source Code . 181 Takeaways . 181 7. Just for the Fun of It . 183 Getting Started with VGA-Displayed Arcade Games . 183 How It Works 184 Loading a Game . 185 Source Code and ROM Files 189 Getting Started with LED Dot Matrix–Displayed Arcade Games 192 How It Works 193 Design 195 Experiments . 197 Source Code . 198 Takeaways . 199 8. Cha-Ching! 201 Getting Started with the Bitcoin Miner 202 How It Works 203 Design 204 Source Code . 207 vi Make: FPGAsTakeaways . 207 9. I Hear You! . 209 Getting Started with the SDR Receiver 210 How It Works 212 Red Pitaya Setup 213 Loading the SDR . 213 Step 1: Copy Red Pitaya SD Card Image . 213 Step 2: Install SDR Applications on PC 214 Step 3: Connect Red Pitaya to the Network . 214 Step 4: Run SDR Applications 214 Source Code . 216 Takeaways . 217 Appendix A. FPGA Boards 219 Appendix B. Papilio AVR Loading . 223 Appendix C. Text and Code Editor 229 Index 231 Index Symbols #define directive, 165 $display, 119 $time, 119 1-Pixel Pac-Man project, 193 ; (semicolons), 51 <= (nonblocking assignment statement), 90 A Add Symbol tool, 175 Altera, xi always blocks, 90, 119 AMBA (Advanced Microcontroller Bus Architecture), 105, 158 analog-to-digital converter (ADC), 212 anode configuration, 82 arcade games project appeal of vintage games, 183 important points, 199 LED dot matrix-displayed, 192-198 VGA-displayed, 183-191 Arduino C program, 164, 168 Arduino shield ecosystem, 3 arithmetic logic unit (ALU), 128 ARM A9 processor, 8 ARM-based SoCs, 158 assign statement, 52, 90 async reset, 53 audio cores, 171 audio generator blocks, 175 AVR (Arduino microcontroller), 162, 223-228 axasm universal assembler, 151 B baud rate clocks, 89 BCD math conversion algorithm, 145 begin statements, 90 behavioral models, 15 binary counters, 34 bit files, xii, 70, 166, 177 Bitcoin mining project background on Bitcoin currency, 201 bill of materials, 202 block diagram, 203 designing in DesignLab, 204 device setup, 202 important points, 207 source code, 207 BitGen bistream generator, 70 blink LEDs concept, 22-25 block diagrams, 12 block memory, regenerating, 141 BoM (Bill of Materials) for Bitcoin mining project, 202 for LED dot matrix-displayed games, 192 231for LED project, 25 for SDR receiver project, 211 for stopwatch project, 83 for VGA-displayed arcade game, 183 for video-audio player, 169 bottom-up design method, 14 BRAM, 189 breadboards, 25, 71, 83 break points, 122 buffers, 41 build phase, 18 bus functional models , 15, 158 bus taps, 40 C C programs, 168 Cadence Design Systems, 103 CARDIAC computer, 125 (see also VTACH project) cathode configuration, 82 CB16CE, 53 chassis-based platforms, 158 circuit verification, 103 (see also test bench method) clock frequency divider circuit, 22 clock frequency experimentation, 75 clock pulse strobes, 86 clock signals, 119 CLR pin, 53 code editors, 229 code reuse, 105 comment text, 49 common cathode vs. common anode configuration, 82 computer-aided design (CAD), 14, 158 concept phase, 11 connection by name, 89 constraints file, creating, 68 copying errors, 187 CORE Generator & Architecture Wizard, 88, 141 counters cascading, 36 coding, 50 complete Verilog code for, 53 defining loops and reset, 52 symbols for, 34 wiring, 35 CPLD (complex programmable logic device), 18, 210 D D Register, 50 D-Flip-Flop (DFF), 50 D2XX driver, 131 debugging, 44 delay control, 118 design flow build phase, 18 concept phase, 11 design phase, 12 overview, 11 run phase, 18 synthesize phase, 17 test phase, 15 design phase, 12 design rule checks (DRC) system, 68 DesignLab audio block addition, 175 benefits of, 160 Bitcoin mining project, 204 creating new projects, 171 creating/loading sketches, 178 downloading, 160 editing designs, 172 implementing/generating bit files, 177 installation, 160 LED dot matrix display experiments, 197 opening example designs, 195 VGA adapter block addition, 175 VGA color control, 179 video-audio player, 169 viewing designs, 196 development tools, 2 device properties, specifying, 29 device under test (DUT), 104, 118 Digilent Pmod Interface Specification, 3 digital clock manager (DCM), 87-90 digital down-converter (DDC), 212 232 Indexdigital frequency synthesizers, 89 DOA (dead on arrival) test, 15, 98 Dr. Dobb, 151 DUO Computing Shield, 175 E Edimax EW7811Un, 213 Elbert V2 features of, 9 modifications for VTACH project, 134-145 setup, 130-134 Emacs text editor, 229 embedded computing devices, 195 end statements, 90 endmodule keyword, 47 EPLD (erasable programmable logic device), 210 error handling, 44 F fabrics defined, 158 standards for, 158 Wishbone Bus Interface Standard, 158 Fingerman, Saul, 125 flat design method, 14 flip-flops, 50 FPGA (field programmable gate array) benefits of, x history of, ix implementation characteristics, 210 FPGA boards design flow for, 11-19 Numato Lab, 8-10 Opal Kelly, 4-6 overview of, 219 Papilio DUO, 2-4 Papilio series, 3 prices of, 1, 3-4, 6, 8, 219 Red Pitaya, 6-8 selecting, 1, 19 Xilinx selection list, 219 Xilinx Zynq, 2 (see also individual boards) FPGA circuit HDL design entry attaching elements with assign statement, 52 compiling code with HDL synthesizer, 53 completed counter circuit Verilog code, 53 counter coding, 50 creating HDL source files, 48 declaring wires, 52 defining counter loop and reset, 52 defining counter variables, 51 defining module ports, 47 ISE HDL editor color codes, 49 logic design elements, 57 naming projects, 45 new project creation, 45 opening new source files, 46 overview, 45 propagation delay, 58 RTL view, 56 selecting preferred language, 45 Technology view, 57 timing tools, 59 Verilog design, 50 FPGA circuit schematic design entry adding binary counters, 34 adding bus taps, 40 adding I/O pin symbols, 43 adding labels, 37 adding output buffers, 41 cascading counters, 36 debugging, 44 default settings, 30 diagram, 42 error handling, 44 implementing (compiling) modules, 44 naming projects, 28 opening new projects, 27 opening new source files, 30 opening schematic drawings, 32 saving work, 42 selecting source types, 31 specifying device properties, 29 wiring counters, 35 zooming in, 33 FPGA Mezzanine Connect (FMC), 1 framebuffers, 179 frequency configuration, 75 Index 233frequency synthesizers, 89 FrontPanel SDK, 5, 66 FTDI CDM drivers, 131 full custom implementation, 210 G Gadget Factory, 159 "garbage in, garbage out" adage, 18 gate array implementation, 210 gedit, 229 general-purpose computing devices, 194 Generate Programming File process, 70 generating enable strobes, 86 GPIO (general purpose I/O), 67, 100 graphical analysis, 122 graphical form, 12 H Hagelbarger, David, 125 hardware description languages (HDLs), 18 "HDL Coding Practices to Accelerate Design Performance", 58 HDL concurrency concept of, 79 important points, 101 7-segment displays, 80 stopwatch concept, 79 stopwatch design, 82-98 HDL form, 2, 12 HDSDR application, 214 Hierarchical Design method, 12, 89 I I/O pins assigning physical, 65-68, 100 constraints file creation, 68 pin mapping table, 68 polarity coding on Elbert V2, 138 remapping Elbert V2, 135 symbols for, 43 I2C serial bus, 12, 107, 117 I2C-Master Core Specification, 107 IDE (integrated development environment), 19 if statement, 52 iMPACT tool, 70 implementation technologies, 210 indicator lights, designing blinking, 22-25 input clock, 22, 66, 80 Institute of Electrical and Electronics Engineers (IEEE), 209 integrated circuits (IC), 156 Intel Corporation, 156 Intel CPU chips, 210 interface connectors, 1 Internet connections, 213-214 IP blocks, 105, 159, 175 ISE HDL editor, 49 ISE Place and Route tool, 43 K Kilby, Jack, 156 L labels, adding to designs, 37 LED dot matrix-displayed arcade games bill of materials, 192 block diagram, 193 designing in DesignLab, 195 LED display experiments, 197 source code, 198 LEDs, designing blinking, 22-25 Linux support, 19 local microcontrollers, 2 Logic Cell Array (LCA), xi loops, 52 Lopes, Alvaro, 170 M Mac support, 19 master devices, 117 Matrixman, 193 meeting timing, 58 234 Indexmemory blocks, regenerating, 141 memory fabric, 158 memory mapping, 194 Mentor Graphics, 103 microcontrollers, 2 Mimas V2, 10 mining pools (Bitcoin), 206 MIT Scratch programming paradigm, 213 ModelSim, 216 module keyword, 47 modules implementing (compiling), 44 instantiating, 89 Moore, Gordon, 156 multi-clock-period signals, 86 N nonblocking assignment statement (<=), 90 Notepad, 229 Numato Lab, 8-10 O OCP, 105, 158 one-clock pulse, 86 1-Pixel Pac-Man project, 193 Opal Kelly assigning physical I/O, 66-68 features of, 4-6 Pins UCF file generator, 70 setup, 72-75 Open Verification Methodology (OVM), 103 open-source IP block libraries, 105 OpenCores library benefits of, 105 downloading I2C controller core, 105 VTACH project, 128 operating precision, 118 ordered connection, 89 oscilloscopes, 8 output buffers, 41 P Pac-Man, 183 Papilio AVR (Arduino microcontroller), 162, 223-228 Papilio DUO features of, 2-4 in Bitcoin mining project, 202 in VGA-displayed arcade game project, 183 setup, 161-169 Papilio FPGA boards, 3 Papilio One 250K, 3 Papilio Wings connectors, 3 path delay, 58 peripheral breadboads, 25 Peripheral Component Interconnect (PCI), 195 peripheral fabric, 158 personal computers (PC), 194 photolithographic manufacturing process, 210 pin mapping table, 68 Pins application, 70 pixels, writing to VGA, 179 PlanAhead environment, 69 PlanAhead tool, 68 PLDs (programmable logic devices), x PLL (phase lock loop), 66, 75 Pmod (Peripheral Module Interface), 3, 5 Pong Demo, 189 port declaration wizard, 47 ports, connecting, 89, 162 printed wiring boards (PWBs), 14, 155 projects arcade games, 183-199 Bitcoin mining, 201-207 CARDIAC/VTACH computer, 125-153 LED blink, 22-77 naming, 28, 45 opening, 27, 45 software-defined radio, 209-217 specifying device properties, 29 stopwatch, 79-101 test bench, 103-124 updating device selection, 134 video-audio player, 155-181 propagation delay, 58 Index 235PSPad, 229 PWRSEL jumper, 162 Python mining script, 206 R rack-based computer systems, 158 radio frequency (RF), 209 Red Pitaya features of, 6-8 Internet connection, 214 SDR loading, 213 setup, 213 refresh rates, 83 reg reserved word, 51 register transistor logic, 17 registers, 50 reset functionality, 52 resistor-transistor logic, 156 reuse, 105 RF (anolog) frontend, 213 RGB adapter block, 193 ROM files, 189 romgen tool, 189 ROMVault installing, 186 running, 188 RTL (register-transfer level) bottom level view, 56 classic synchronous HDL logic design, 56 defined, 17 ISE schematic viewer, 54 run phase, 18 S Sbuild2, 68 .sch files, 58 schematic drawings, 2, 14 schematic symbol library, 33 schematic-to-HDL conversion, 58 scope probes, 6 SDR (software-defined radio) project antenna setup, 211 bill of materials, 211 block diagram, 212 how it works, 212 important points, 217 loading, 213 Red Pitaya setup, 213 SDR benefits, 209 SDR definitions, 209 source code, 216 tutorial page, 212 semicolons (;), 51 serial clock line (SCL), 108 serial data line (SDA), 108 7-segment displays how they work, 80 Verilog code for, 90 VTACH project, 128 SHM (Simulation History Manager), 122 SID (sound interface device), 171 signal generators, 8 simulation test benefits of, 60 build process, 65 creating constraints file, 68 forcing clock and reset signals, 61 opening, 60 programming target device, 70 stopwatch design, 98 VTACH project, 145-150 sketches, 164, 168, 178 slave devices, 117 smartphone block diagram, 157 SoC design architecture, 157 functional block diagram approach, 155 history of SoCs, 155 important points, 181 Moore's law and, 156 Papilio DUO setup, 161-169 using DesignLab, 160 video-audio player, 169, 171-181 SoC development flow blink LEDs concept, 22-25 BoM (Bill of Materials), 25 clock frequency experimentation, 75 design overview, 25 diagram, 21 236 IndexFPGA circuit HDL design entry, 45-60 FPGA circuit schematic design entry, 27-44 implementation technologies, 210 important points, 76 Opal Kelly setup, 72-75 overview, 21 peripheral breadboard, 25 simulation, 60-71 Xilinx ISE WebPACK installation, 23-25 soft designs, 165 soft IP libraries, 105 Software-Controlled Sound Generator (SSG), 171 Space Invaders, 183 "Spartan-6 Libraries Guide for Schematic Designs", 35 Spartan 3A, 128 Spartan XC3S50A, 10 Spartan-6 LX9, 10 spectrum analyzers, 8 standard cell implementation, 210 stimuli (inputs), 104 stopwatch project BoM (Bill of Materials), 83 build process, 100 concept for, 79 design overview, 82 digital clock manager (DCM), 87-90 FPGA circuit for, 84 peripheral breadboard, 83 7-segment display for, 80 simulation test, 98 Verilog code and concurrency, 90-98 Stratum proxy, 206 sync reset, 53 Synopsys, 105 synthesis tool, 17 synthesize phase, 17 synthesized clocks, 89 sysclk period, 100 system clock, 22 Szczys, Mike, 193 T technologies for implementation, 210 Technology view, 57 test bench method adding files for simulation, 112 basics of, 15, 103 block diagram of I2C core, 116 clocks and resets, 119 code examination in iSim tool, 117 code reuse and, 105 components and terminology, 104 displaying results, 119 documentation review, 107 downloading I2C controller core, 105 examining code using break points, 122 grouping commands with tasks, 119 important points, 124 instantiating DUT and generators, 118 instantiation of wrapper, 104 RTL file review, 109 viewing data with waveforms, 122 test fixture (see test bench method) test phase, 15 Texas Instruments, 156 text editors, 229 time scale, 118 timing tools, 59 tool licenses, 2 transistors, 156 triggers, 50 U unit under test (UUT), 15, 104 universal cross assembler, 151 USB WiFi dongle, 213 USB-Micro connector, 162 USB-Mini connector, 162 user constraints file (UCF), 68, 135 V validation phase, 15 VCD (Value Change Dump) format, 122 Verilog code example, 13 code for FPGA 7-segment display, 90-98 Index 237coding circuit building blocks, 50 combining elements, 52 compiling code, 53 creating module source file, 46 declaring wires, 52 defining counter loop and reset, 52 defining module ports, 47 modules in, 50, 89 selecting as preferred language, 45 semicolon use in, 51 test bench example, 103 time scale and operating precision, 118 VGA adapters, 171, 175 VGA-displayed arcade games bill of materials, 183 block diagram, 184 how it works, 185 loading games, 185-189 source code and ROM files, 189 VHDL ISE HDL editor color codes, 49 tools supporting, 2 vs. Verilog, 76 vi text editor, 229 video-audio player project bill of materials, 169 block diagram, 169 designing in DesignLab, 171-181 how it works, 170 vintage arcade theme, 183 virtual breadboard sandbox, 6 virtual testing environments, 103 Visual Programming tool, 213 VTACH project building and running, 150 design illustration, 128 downloading from OpenCores, 128 Elbert V2 modifications, 134-145 Elbert V2 setup, 130-134 generating your design, 145 important points, 153 opening, 129 programing and assembler, 151 resource pages, 128 simulation, 145-150 W waveforms, 98, 122 Waxwing, 10, 131 WiFi connections, 213 Williams, Al, 151 Wishbone interface, 108, 158, 171 X XEM6002 (see Opal Kelly) Xilinx FPGA boards, 219 Xilinx ISE WebPACK CORE Generator & Architecture Wizard, 88 creating HDL source files, 48 FPGA circuit HDL design entry, 45-60 FPGA circuit schematic design entry, 30-44 HDL editor color codes, 49 installation, 23-25 opening projects, 27, 45 Place and Route tool, 43 port declaration wizard, 47 Red Pitaya support, 216 ROM file handling, 189 Schematic Viewer, 54 schematic-to-HDL conversion, 58 timing tools, 59 wave form viewer, 98 Xilinx ISim simulator, 112, 117 Xilinx Spartan-6 XC6SLX9, 3, 4 Xilinx XC 2000, xi Xilinx XC3S250, 3 Xilinx Zynq, 2, 6 Y Yamaha YM2149, 171 Z ZPUino, 165, 170, 193
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